----------------------------------------------------------------------- # SFFS Operating System Porting XXXX MUST NOT DOUBLEFUND! (resolved: no longer a duplicate of bug #983) XXXX to continue the work done by VanTosh under NGI POINTER with PowerEL porting to SFFS, gentoo and debian need a PowerPC64 "SFFS" port as well, and PowerEL needs additional work. this will be suitable not just for Libre-SOC but also Microwatt and also the Freescale/NXP E5500 64-bit CPU (with emulation of v3.0 already present in linux kernel) https://bugs.libre-soc.org/show_bug.cgi?id=999 EUR: 10,000 ----------------------------------------------------------------------- # improvements of Libre-SOC core support on FPGA boards mostly this is the ls2 peripheral fabric which needs peripherals and platforms improving, generally this milestone is to cover improving Libre-SOC core support on FPGA boards. URL: https://bugs.libre-soc.org/show_bug.cgi?id=1037 EUR: 6,000 -------------------------------------------------------------------- # redesign dct and fft integer twin butterfly instructions the integer dct and fft instructions need redesigning and full development and integration with the FFT and DCT REMAP subsystem. if possible they should be integrated into the planned 2D DCT/FFT subsystem of bug #963 as well. https://bugs.libre-soc.org/show_bug.cgi?id=1206 EUR: 6,000 ----------------------------------------------------------------------- # Formal Proof for LDSTCompUnit is needed the ALU CompUnit Formal Proof was very successful and tracked down a critical bug. a similar proof is needed for LDSTCompUnit. https://bugs.libre-soc.org/show_bug.cgi?id=1036 EUR: 3,000 ----------------------------------------------------------------------- # Implement PO9 changeover and associated tasks As part of bug #952 - the NLnet 2022 OPF ISA WG Grant 2022-08-051 - it was established that PO9 is a candidate for use by SVP64 instead of shoe-horning into PO1. That now needs to be implemented along-side its knock-on implications in ISACaller, the insndb, and binutils. Additionally there are some instructions easy to implement (LD/ST-post-update) that are beneficial to performance, that again came out of the OPF RFC Feedback process. URL: https://bugs.libre-soc.org/show_bug.cgi?id=1150 EUR: 10,000 ----------------------------------------------------------------------- # Addition of ALUs and pipelines for Draft ISA instructions Unit tests and ISACaller Simulator implementation exists for the various Draft ISA instructions to be proposed under bug #952 (NLnet 2022-08-051) but HDL for inclusion in Libre-SOC Core does not yet exist. There are approximately 50 new IEEE754 Transcendental instructions to be added, several bitmanip instructions, and the BigInt 3-in 2-out (64-bit carry) instructions. URL: https://bugs.libre-soc.org/show_bug.cgi?id=1026 EUR: 8,000 ----------------------------------------------------------------------- # XLEN unit tests. The Simulator needs a huge number of Unit tests for elwidth overrides as every existing 64-bit unit test now needs to be joined by 8-bit, 16-bit and 32-bit tests. URL: https://bugs.libre-soc.org/show_bug.cgi?id=1032 EUR: 4,000 ----------------------------------------------------------------------- # Implementation and enhancement of "Test API" add microwatt, cavatools, FPGA and "standard Makefile" targets for running as raw binaries in a VM/native/FPGA. related to NLnet Grant OPF ISA 2022-08-051 cavatools. the purpose of the "Test" API is to make it possible to compare unit test results automatically against different implementations. URL: https://bugs.libre-soc.org/show_bug.cgi?id=1033 EUR: 2,500 ----------------------------------------------------------------------- # Continuation of instruction database and binutils the instruction database (machine-generation) needs continuation particularly for CR and Branch operations. note this is a duplicate of bug #976 which has been marked as resolved/fixed, avoid "missing specifiers" (what bug #976 covered) under this task unless further work is needed https://bugs.libre-soc.org/show_bug.cgi?id=1003 EUR: 10,500 ----------------------------------------------------------------------- # Implement Scalar Power ISA v3.1 instructions in ISACaller Power ISA has moved on to v3.1, and if Draft SVP64 is to be accepted in a future version of Power it must be on the future version (not v3.0). URL: https://bugs.libre-soc.org/show_bug.cgi?id=1035 Budget: 7000 ----------------------------------------------------------------------- # Implement "necessary" additions to SVP64 and Scalar Power ISA In the OPF ISA WG Grant 2022-08-051 there is considerable work to be done in submitting almost 100 instructions via the OPF's External RFC Process. Adding to this workload is greatly undesirable however under certain circumstances may prove necessary, was already planned, or may be demonstrably greatly beneficial. For example a 2D DCT Mode for REMAP was planned, as was the design and addition of Integer DCT and FFT Butterfly instructions. Additionally some 64-bit versions of SVP64's setvl and REMAP instructions have been planned for some time, including extending Matrix REMAP to do both inner and outer product, and the CRweird and ternary/binary instructions have to be implemented. Note that the key difference between this Milestone and the OPF ISA WG Grant 2022-08-051 is that everything under 2022-08-051 has already been designed and implemented under the SVP64 ISACaller Simulator. This Milestone brings the necessary additions up to a point where 2022-08-051 can take over. Additionally the python-based pypowersim needs to be made easier to compile for x86: presently it runs best only on ppc64. This will allow development of SVP64 and Power ISA additions to be easier. URL: https://bugs.libre-soc.org/show_bug.cgi?id=1027 Budget: 30,000 ----------------------------------------------------------------------- # add hardware-cycle-accurate statistical modelling to ISACaller for an in-order core Hardware-cycle-accurate statistics are needed but it will take some effort to add to cavatools. therefore a model needs to be added to ISACaller which allows some basic performance estimates. This task is not part of the cavatools grant 2021-08-071. It can be achieved much more immediately. URL: https://bugs.libre-soc.org/show_bug.cgi?id=1039 Budget: 3000 -----------------------------------------------------------------------